Many integrated circuit (IC) memory devices conventionally include static random access memory (SRAM). Conventional SRAM is based on four-transistor memory cells (4T SRAM cells) or six-transistor memory cells (6T SRAM cells) that are compatible with conventional memory elements, such as complementary metal-oxide-semiconductor (CMOS) devices, operate at low voltage levels, and perform at relatively high speeds. However, conventional SRAM consumes a large cell area that limits high-density design of SRAM.
In attempts to reduce the area of IC memory devices, high-density, low-voltage SRAM cells including four layers of alternating n- and p-type semiconductive material, often referred to as a “thin capacitively-coupled thyristor (TCCT)” have been fabricated. As used herein, the term “thyristor,” means and includes a bi-stable, three-terminal device that includes a four layer structure including a p-type anode region, an n-type base, a p-type base, and an n-type cathode region arranged in a p-n-p-n configuration. The thyristor may include two main terminals, an anode and a cathode. Further, a control terminal, often referred to as the “gate,” may be operatively adjacent to the p-type material nearest the cathode. Thyristor-based random access memory (T-RAM) cells demonstrate faster switching speeds and lower operating voltages in comparison to conventional SRAM cells.
A thyristor in a memory device may be turned on by biasing the gate so that a p-n-p-n channel conducts a current. Once the device is turned on, often referred to as “latched,” the thyristor does not require the gate to be biased to maintain the current conducted between the cathode and the anode. Instead, it will continue to conduct until a minimum holding current is no longer maintained between the anode and cathode, or until the voltage between the anode and the cathode is reversed. Accordingly, the thyristor may function as a switch or diode capable of being switched between an “on” state and an “off” state.